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Page 128 Epson Research and Development
Vancouver Design Center
S1D13708 Hardware Functional Specification
X39A-A-001-02 Issue Date: 02/03/07
bits 6-0 Horizontal Display Period Bits [6:0]
These bits specify the LCD panel Horizontal Display period, in 8 pixel resolution. The
Horizontal Display period should be less than the Horizontal Total to allow for a sufficient
Horizontal Non-Display period.
Horizontal Display Period in number of pixels = ((REG[14h] bits 6:0) + 1) × 8
Note
For passive panels, HDP must be a minimum of 32 pixels and can be increased by mul-
tiples of 16. For TFT panels, HDP must be a minimum of 16 pixels and can be increased
by multiples of 8.
Note
For panel AC timing and timing parameter definitions, see Section 6.4, “Display Inter-
face” on page 68.
bits 9-0 Horizontal Display Period Start Position Bits [9:0]
These bits specify a value used in the calculation of the Horizontal Display Period Start
Position (in 1 pixel resolution) for TFT, ‘Direct’ HR-TFT and ‘Direct’ D-TFD panels. For
passive LCD panels these bits must be set to 00h.
To calculate the Horizontal Display Period Start Position (HDPS) an offset which depends
on the panel type is required. For further information on calculating the HDPS, see the
specific panel AC timing in Section 6.4, “Display Interface” on page 68.
Note
This register must be programmed such that the following formula is valid.
HDPS + HDP < HT
Horizontal Display Period Register
REG[14h] Read/Write
n/a Horizontal Display Period Bits 6-0
76543210
Horizontal Display Period Start Position Register 0
REG[16h] Read/Write
Horizontal Display Period Start Position Bits 7-0
76543210
Horizontal Display Period Start Position Register 1
REG[17h] Read/Write
n/a
Horizontal Display Period
Start Position Bits 9-8
7 6 5 4 3 210