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Page 12 Epson Research and Development
Vancouver Design Center
S1D13708 13708CFG Configuration Program
X39A-B-001-01 Issue Date: 01/11/16
PWMCLK These controls configure various PWMCLK settings.
The PWMCLK is the internal clock used by the Pulse
Width Modulator for output to the panel.
Enable When this box is checked, the PWMCLK circuitry is
enabled.
Force High The signal PWMOUT is forced high when this box is
checked. When not checked, PWMOUT will be low if
PWM is not enabled or will change state according to
the configured values when PWM is enabled.
Source Selects the PWMCLK source. Possible sources include
CLKI, CLKI2 and XTAL. Note that CLKI2 is available
for a PWMCLK source clock if PCLK does not use
XTAL. Also note that XTAL is available for a
PWMCLK source clock if PCLK does not use CLKI2.
Divide Specifies the divide ratio for the clock source. The
divide ratio is applied to the PWMCLK source to derive
PWMCLK.
Note
After this divide is applied, PWMCLK is further
divided by 256 to achieve the final PWMCLK
frequency.
Timing This field shows the actual PWMCLK frequency used
by the configuration process.
Duty Cycle Selects the number of cycles that PWMOUT is high out
of 256 clock periods.
Contrast Voltage Pulse These controls configure various Contrast Voltage
(CV) Pulse settings. The CV Pulse is provided for
panels which support the contrast voltage function.
Enable When this box is checked, the CV Pulse circuitry is
enabled.
Force High The signal CVOUT is forced high when this box is
checked. When not checked, CVOUT will be low if CV
is not enabled or will change state according to the
configured values when CV is enabled.
Source The CV Pulse uses the same source clock as the
PWMCLK.