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Epson Research and Development Page 9
Vancouver Design Center
Interfacing to the Motorola MCF5307 "ColdFire" Microprocessor S1D13708
Issue Date: 01/11/25 X39A-G-010-01
Figure 2-1: “MCF5307 Memory Read Cycle,” illustrates a typical memory read cycle on
the MCF5307 system bus.
Figure 2-1: MCF5307 Memory Read Cycle
Figure 2-2: “MCF5307 Memory Write Cycle,” illustrates a typical memory write cycle on
the MCF5307 system bus.
Figure 2-2: MCF5307 Memory Write Cycle
2.1.3 Burst Cycles
Burst cycles are very similar to normal cycles, except that they occur as a series of four
back-to-back, 32-bit memory reads or writes. The TIP
(Transfer In Progress) output is
asserted continuously through the burst. Burst memory cycles are mainly intended to fill
A[31:0]
D[31:0]
BWE[1:0], TT[1:0]
TS
TA
BCLK0
Wait StatesTransfer Start Transfer Next Transfer
Sampled when TA low
R/W
Complete Starts
TIP
A[31:0]
D[31:0]
BWE[1:0], TT[1:0]
TS
TA
BCLK0
Wait StatesTransfer Start
R/W
Valid
Transfer Next Transfer
Complete Starts
TIP