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Page 38 Epson Research and Development
Vancouver Design Center
S1D13708 Hardware Functional Specification
X39A-A-001-02 Issue Date: 02/03/07
4.4 Summary of Configuration Options
Table 4-8: Summary of Power-On/Reset Options
S1D13708
Configuration
Input
Power-On/Reset State
10
CNF4,CNF[2:0]
Select host bus interface as follows:
CNF4 CNF2 CNF1 CNF0 Host Bus
1000SH-4/SH-3 interface, Big Endian
0000SH-4/SH-3 interface, Little Endian
1001MC68K #1, Big Endian
0001Reserved
1010MC68K #2, Big Endian
0010Reserved
1011Generic #1, Big Endian
0011Generic #1, Little Endian
1100Reserved
0100Generic #2, Little Endian
1101REDCAP2, Big Endian
0101Reserved
1110DragonBall (MC68EZ328/MC68VZ328), Big Endian
0110Reserved
1111Indirect Interface, Big Endian
0111Indirect Interface, Little Endian
CNF3 Configure GPIO pins as inputs at power-on
Configure GPIO pins as outputs at power-on (for use
by HR-TFT/D-TFD/TFT Type 2/TFT Type 3 when
selected)
CNF5 WAIT# is active high WAIT# is active low
CNF[7:6]
BCLK Source (CLKI/XTAL) to BCLK divide select:
Note: XTAL should only be used when configured for Indirect Interface (CNF[2:0] = 111).
CNF7 CNF6 BCLK Divide Ratio
00 1 : 1
01 2 : 1
10 3 : 1
11 4 : 1