Page 16 Epson Research and Development
Vancouver Design Center
S1D13708 Interfacing to the Motorola RedCap2
X39A-G-014-01 Issue Date: 01/11/06
4.5 REDCAP2 Chip Select Configuration
In this example, Chip Select 1 controls the S1D13708. The following options are selected
in the CS1 Control Register.
• CSEN = 1 — Chip Select function enabled.
• WP = 0 — writes allowed.
• SP = 0 — user mode access allowed.
• DSZ = 10 — 16-bit Port.
• EBC = 0 — assert EB0-1
for both reads and writes.
• WEN = 1 — EB0-1
negated half a clock earlier during write cycle.
•OEA = 1 — OE
asserted half a clock later during a read cycle.
• CSA = 0 — Chip Select asserted as early as possible. No idle cycle inserted between
back-to-back external transfers.
• EDC = 1 — an idle cycle is inserted after a read cycle for back-to-back external trans-
fers, unless the next cycle is a read cycle to the same CS
bank.
• WWS = 0 — same length for reads and writes.
