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Epson Research and Development Page 167
Vancouver Design Center
Hardware Functional Specification S1D13708
Issue Date: 02/03/07 X39A-A-001-02
bits 5-0 Partial Area 1 X Start Position Bits [5:0]
These bits specify the X Start Position of Partial Area 1 in 8 pixel resolution. This register
is used for the TFT Type 3 Interface and has no effect for all other panel interfaces.
bits 5-0 Partial Area 1 Y Start Position Bits [5:0]
These bits specify the Y Start Position of Partial Area 1 in 8 line resolution. This register is
used for the TFT Type 3 Interface and has no effect for all other panel interfaces.
bits 5-0 Partial Area 1 X End Position Bits [5:0]
These bits specify the X End Position of Partial Area 1 in 8 pixel resolution. This register
is used for the TFT Type 3 Interface and has no effect for all other panel interfaces.
bits 5-0 Partial Area 1 Y End Position Bits [5:0]
These bits specify the Y End Position of Partial Area 1 in 8 line resolution. This register is
used for the TFT Type 3 Interface and has no effect for all other panel interfaces.
TFT Type 3 Partial Area 1 X Start Position Register
REG[E6h] Read/Write
n/a Partial Area 1 X Start Position bits 5-0
7 6543210
TFT Type 3 Partial Area 1 Y Start Position Register
REG[E7h] Read/Write
n/a Partial Area 1 Y Start Position bits 5-0
7 6543210
TFT Type 3 Partial Area 1 X End Position Register
REG[E8h] Read/Write
n/a Partial Area 1 X End Position bits 5-0
7 6543210
TFT Type 3 Partial Area 1 Y End Position Register
REG[E9h] Read/Write
n/a Partial Area 1 Y End Position bits 5-0
7 6543210