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Epson Research and Development Page 9
Vancouver Design Center
Interfacing to the Motorola RedCap2 S1D13708
Issue Date: 01/11/06 X39A-G-014-01
Figure 2-1: “REDCAP2 Memory Read Cycle” on page 9 illustrates a typical memory read
cycle on the REDCAP2 bus.
Figure 2-1: REDCAP2 Memory Read Cycle
Figure 2-2: “REDCAP2 Memory Write Cycle” on page 9 illustrates a typical memory
write cycle on the REDCAP2 bus.
Figure 2-2: REDCAP2 Memory Write Cycle
A[21:0]
CS
CLK
D[15:0]
R/W
OE, EB0-1
A[21:0]
CS
CLK
D[15:0]
R/W
OE, EB0-1