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Page 14 Epson Research and Development
Vancouver Design Center
S1D13708 Interfacing to the NEC VR4102 / VR4111 Microprocessors
X39A-G-007-01 Issue Date: 01/11/05
4.3 NEC VR4102/VR4111 Configuration
The NEC VR4102/4111 provides the internal address decoding necessary to map an
external LCD controller. Physical address 0A00_0000h to 0AFF_FFFFh (16M bytes) is
reserved for an external LCD controller by the NEC VR4102/4111.
The S1D13708 is a memory mapped device. The S1D13708 uses two 128K byte blocks
which are selected using ADD17 from the NEC VR4102/4111 (ADD17 is connected to the
S1D13708 M/R# pin).The internal registers occupy the first 128K bytes block and the 80K
byte display buffer occupies the second 128K byte block.
The starting address of the S1D13708 internal registers is located at 0A00_0000h and the
starting address of the display buffer is located at 0A02_0000h. These blocks are aliased
over the entire 16M byte address space.
Note
If aliasing is not desirable, the upper addresses must be fully decoded.
The NEC VR4102/VR4111 has a 16-bit internal register named BCUCNTREG2 located at
0B00_0002h. It must be set to the value of 0001h which indicates that LCD controller
accesses use a non-inverting data bus.
The 16-bit internal register named BCUCNTREG1 (located at 0B00_0000h) must have bit
D[13] (ISA/LCD bit) set to 0. This reserves 16M bytes (from 0A00_0000h to
0AFF_FFFFh) for use by the LCD controller and not as ISA bus memory space.