Epson S1D13708 Camera Accessories User Manual


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S1D13708 Register Summary X39A-R-001-01
Pa
g
e 2 01/01/25
GENERAL IO PINS REGISTERS
PWM CLOCK AND CV PULSE CONFIGURATION REGISTERS
EXTENDED REGISTERS
Notes
1 REG[00h] These bits are used to identify the SED13708. For the SED13708, the product code should be
001101.
2 REG[04h] Memory Clock Configuration Register
REG[A2h] S
OFTWARE
R
ESET
R
EGISTER
RW
Reserved n/a
Software
Reset (WO)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
REG[A3h] R
ESERVED
RW
Reserved n/a
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
REG[A4h] S
CRATCH
P
AD
R
EGISTER
0 RW
Scratch Pad bits 7-0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
REG[A5h] S
CRATCH
P
AD
R
EGISTER
1 RW
Scratch Pad 15-8
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
REG[A8h] G
ENERAL
P
URPOSE
IO P
INS
C
ONFIGURATION
R
EGISTER
0 RW
n/a
GPIO6 Pin
IO Config
GPIO5 Pin
IO Config
GPIO4 Pin
IO Config
GPIO3 Pin
IO Config
GPIO2 Pin
IO Config
GPIO1 Pin
IO Config
GPIO0 Pin
IO Config
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
REG[A9h] G
ENERAL
P
URPOSE
IO P
INS
C
ONFIGURATION
R
EGISTER
1 RW
GPIO Pin
Input Enable
Reserved
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
REG[ACh] G
ENERAL
P
URPOSE
IO P
INS
S
TATUS
/C
ONTROL
R
EGISTER
0 RW
n/a
GPIO6 Pin
IO Status
GPIO5 Pin
IO Status
GPIO4 Pin
IO Status
GPIO3 Pin
IO Status
GPIO2 Pin
IO Status
GPIO1 Pin
IO Status
GPIO0 Pin
IO Status
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
REG[ADh] GENERAL PURPOSE IO PINS STATUS/CONTROL REGISTER 1 RW
GPO Control Reserved
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
REG[B0h] PWM C
LOCK
/ CV P
ULSE
C
ONTROL
R
EGISTER
RW
PWM Clock
Force High
n/a
PWM Clock
Enable
CV Pulse
Force High
CV Pulse
Burst Status
(RO)
CV Pulse
Burst Start
CV Pulse
Enable
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
REG[B1h] PWM CLOCK / CV PULSE CONFIGURATION REGISTER
9,10
RW
PWM Clock Divide Select bits 3-0 CV Pulse Divide Select bits 2-0
PWMCLK
Source
Select
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
REG[B2h] CV P
ULSE
B
URST
L
ENGTH
R
EGISTER
RW
CV Pulse Burst Length bits 7-0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
REG[B3h] PWMOUT D
UTY
C
YCLE
R
EGISTER
11
RW
PWMOUT Duty Cycle bits 7-0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
REG[C0h] MEMORY ACCESS POINTER 0 RW
Memory Access Pointer bits 7-0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
REG[C1h] MEMORY ACCESS POINTER 1 RW
Memory Access Pointer bits 15-8
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
REG[C2h] MEMORY ACCESS POINTER 2 RW
n/a
Memory
Access
Pointer
bit 16
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
REG[C4h] MEMORY ACCESS START RW
n/a
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
REG[C5h] EXTENDED PANEL TYPE REGISTER RW
n/a
Extended Panel Type
bits 1-0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
REG[C6h] M
EMORY
A
CCESS
S
ELECT
R
EGISTER
RW
n/a
Memory
Access
Select
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
REG[C7h] I
NK
T
RANSPARENT
R
EGISTER
0 RW
Ink Transparent bits 7-0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
REG[C8h] I
NK
T
RANSPARENT
R
EGISTER
1 RW
Ink Transparent bits 15-8
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
REG[C9h] I
NK
L
AYER
R
EGISTER
RW
Ink Layer
Enable
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
REG[CAh] OSCP CONFIGURATION REGISTER RW
n/a OSCP Enable bits 1-0 n/a
BCLK
Source
Select
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
REG[CBh] TFT D
ATA
C
OMPARE
I
NVERT
E
NABLE
R
EGISTER
RW
n/a
Data
Compare
Invert
Enable
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
REG[D0h] TFT T
YPE
2 VCLK C
ONFIGURATION
R
EGISTER
RW
n/a VCLK Hold bits 1-0 n/a VCLK Setup bits 1-0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
REG[D1h] TFT TYPE 2 AP CONFIGURATION REGISTER
RW
POL Type n/a AP Pulse Width bits 2-0 n/a AP Rising Position bits 1-0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
REG[D4h] TFT TYPE 3 CONTROL SIGNAL ENABLE REGISTER RW
PDME
Control
XSTBY
Control
XOHV
Control
XRESV
Control
XRESH
Control
PCLK2
Enable
PCLK1
Enable
n/a
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
REG[D5h] TFT TYPE 3 OE RISING EDGE POSITION REGISTER RW
OE Rising Edge Position bits 7-0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
REG[D6h] TFT TYPE 3 OE PULSE WIDTH REGISTER RW
OE Pulse Width bits 7-0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
REG[D7h] TFT TYPE 3 POL TOGGLE POSITION REGISTER RW
POL Toggle Position bits 7-0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
REG[D8h] TFT T
YPE
3 VCOM T
OGGLE
P
OSITION
R
EGISTER
RW
VCOM Toggle Position bits 7-0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
REG[D9h] TFT T
YPE
3 CPV P
ULSE
W
IDTH
R
EGISTER
RW
CPV Pulse Width bits 7-0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
REG[DAh] TFT TYPE 3 XOEV RISING EDGE POSITION REGISTER RW
XOEV Rising Edge Position bits 7-0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
REG[DBh] TFT TYPE 3 XOEV GPIO5 FALLING EDGE POSITION REGISTER RW
XOEV Falling Edge Position bits 7-0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
REG[DCh] TFT T
YPE
3 PCLK D
IVIDE
R
EGISTER
RW
n/a
PCLK2 Divide Rate
bits 1-0
PCLK1 Divide Rate bits 3-0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
REG[E0h] TFT TYPE 3 PARTIAL MODE DISPLAY AREA CONTROL REGISTER RW
n/a
Partial Mode
Display
Enable
Parial Mode
Display
Type Select
Area 2
Display
Enable
Area 1
Display
Enable
Area 0
Display
Enable
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
REG[E1h] TFT T
YPE
3 P
ARTIAL
M
ODE
D
ISPLAY
R
EFRESH
C
YCLE
R
EGISTER
RW
n/a Partial Mode Display Refresh Cycle bits 5-0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
REG[E2h] TFT TYPE 3 PARTIAL AREA 0 X START POSITION REGISTER RW
n/a Partial Area 0 X Start Position bits 5-0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
REG[E3h] TFT TYPE 3 PARTIAL AREA 0 Y START POSITION REGISTER RW
n/a Partial Area 0 Y Start Position bits 5-0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
REG[E4h] TFT TYPE 3 PARTIAL AREA 0 X END POSITION REGISTER RW
n/a Partial Area 0 X End Position bits 5-0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
REG[E5h] TFT TYPE 3 PARTIAL AREA 0 Y END POSITION REGISTER RW
n/a Partial Area 0 Y End Position bits 5-0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
REG[E6h] TFT TYPE 3 PARTIAL AREA 1 X START POSITION REGISTER RW
n/a Partial Area 1 X Start Position bits 5-0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
REG[E7h] TFT T
YPE
3 P
ARTIAL
A
REA
1 Y S
TART
P
OSITION
R
EGISTER
RW
n/a Partial Area 1 Y Start Position bits 5-0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
REG[E8h] TFT T
YPE
3 P
ARTIAL
A
REA
1 X E
ND
P
OSITION
R
EGISTER
RW
n/a Partial Area 1 X End Position bits 5-0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
REG[E9h] TFT T
YPE
3 P
ARTIAL
A
REA
1 Y E
ND
P
OSITION
R
EGISTER
RW
n/a Partial Area 1 Y End Position bits 5-0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
REG[EAh] TFT T
YPE
3 P
ARTIAL
A
REA
2 X S
TART
P
OSITION
R
EGISTER
RW
n/a Partial Area 2 X Start Position bits 5-0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
REG[EBh] TFT T
YPE
3 P
ARTIAL
A
REA
2 Y S
TART
P
OSITION
R
EGISTER
RW
n/a Partial Area 2 Y Start Position bits 5-0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
REG[ECh] TFT TYPE 3 PARTIAL AREA 2 X END POSITION REGISTER RW
n/a Partial Area 2 X End Position bits 5-0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
REG[EDh] TFT TYPE 3 PARTIAL AREA 2 Y END POSITION REGISTER RW
n/a Partial Area 2 Y End Position bits 5-0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
REG[F0h] TFT TYPE 3 COMMAND 0 STORE REGISTER 0 RW
Command 0 Store bits 7-0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
REG[F1h] TFT T
YPE
3 C
OMMAND
0 S
TORE
R
EGISTER
1 RW
n/a Command 0 Store bits 11-8
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
REG[F2h] TFT T
YPE
3 C
OMMAND
1 S
TORE
R
EGISTER
0 RW
Command 1 Store bits 7-0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
REG[F3h] TFT TYPE 3 COMMAND 1 STORE REGISTER 1 RW
n/a Command 1 Store bits 11-8
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
REG[F4h] TFT TYPE 3 COMMAND SEND REQUEST REGISTER RW
n/a
Command
Send
Request
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
REG[F5h] SOURCE DRIVER IC NUMBER REGISTER RW
n/a
Source Driver IC Number
bits 1-0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
MCLK Divide Select Bits BCLK to MCLK Frequency Ratio
00 1:1
01 2:1
10 3:1
11 4:1
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