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Epson Research and Development Page 31
Vancouver Design Center
Hardware Functional Specification S1D13708
Issue Date: 02/03/07 X39A-A-001-02
WE1# I B2 PIC IOVDD 1
This input pin has multiple functions.
• For Generic #1, this pin inputs the write enable signal for the
upper data byte (WE1#).
• For Generic #2, this pin inputs the byte enable signal for the
high data byte (BHE#).
• For SH-3/SH-4, this pin inputs the write enable signal for data
byte 1 (WE1#).
• For MC68K #1, this pin inputs the upper data strobe (UDS#).
• For MC68K #2, this pin inputs the data strobe (DS#).
• For REDCAP2, this pin inputs the byte enable signal for the
D[15:8] data byte (EB0
).
• For DragonBall, this pin inputs the byte enable signal for the
D[15:8] data byte (UWE).
• For Indirect (Mode 68), this pin inputs the byte enable signal for
the D[15:8] data byte (EBU).
• For Indirect (Mode 80), this pin inputs the write enable signal for
data byte 1 (WRU#).
See Table 4-9: “Host Bus Interface Pin Mapping,” on page 39
for
summary.
CS# I C2 PIC IOVDD 1
Chip select input. See Table 4-9: “Host Bus Interface Pin Mapping,”
on page 39
for summary.
M/R# I K7 PIC IOVDD 0
This input pin is used to select between the display buffer and
register address spaces of the S1D13708. M/R# is set high to
access the display buffer and low to access the registers. See Table
4-9: “Host Bus Interface Pin Mapping,” on page 39
for summary.
BS# I J7 PIC IOVDD 1
This input pin has multiple functions.
• For Generic #1, this pin must be tied to IO V
DD
.
• For Generic #2, this pin must be tied to IO V
DD
.
• For SH-3/SH-4, this pin inputs the bus start signal (BS#).
• For MC68K #1, this pin inputs the address strobe (AS#).
• For MC68K #2, this pin inputs the address strobe (AS#).
• For REDCAP2, this pin must be tied to IO V
DD
.
• For DragonBall, this pin must be tied to IO V
DD
.
• For Indirect (Mode 68), this pin selects the Indirect Interface For
Mode 68, this pin is tied to V
SS
.
• For Indirect (Mode 80), this pin selects the Indirect Interface For
Mode 80, this pin is tied to IO V
DD
.
See Table 4-9: “Host Bus Interface Pin Mapping,” on page 39
for
summary.
Table 4-3: Host Interface Pin Descriptions
Pin Name Type
PFBGA
Pin #
Cell
IO
Voltage
RESET
# State
Description