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Epson Research and Development Page 163
Vancouver Design Center
Hardware Functional Specification S1D13708
Issue Date: 02/03/07 X39A-A-001-02
bits 7-0 CPV Pulse Width Bits [7:0]
These bits specify the pulse width of the CPV signal in 2 pixel resolution. This register is
used for the TFT Type 3 Interface and has no effect for all other panel interfaces.
bits 7-0 XOEV Rising Edge Position Bits [7:0]
These bits specify the rising edge position of the XOEV signal in 2 pixel resolution. This
register is used for the TFT Type 3 Interface and has no effect for all other panel inter-
faces. The value of this register must be greater than zero.
bits 7-0 XOEV Falling Edge Position Bits [7:0]
These bits specify the falling edge position of the XOEV signal in 2 pixel resolution. This
register is used for the TFT Type 3 Interface and has no effect for all other panel inter-
faces.
TFT Type 3 CPV Pulse Width Register
REG[D9h] Read/Write
CPV Pulse Width bits 7-0
76543210
TFT Type 3 XOEV Rising Edge Position Register
REG[DAh] Read/Write
XOEV Rising Edge Position bits 7-0
76543210
TFT Type 3 XOEV Falling Edge Position Register
REG[DBh] Read/Write
XOEV Falling Edge Position bits 7-0
76543210