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Epson Research and Development Page 13
Vancouver Design Center
Interfacing to the Motorola MCF5307 "ColdFire" Microprocessor S1D13708
Issue Date: 01/11/25 X39A-G-010-01
4 MCF5307 To S1D13708 Interface
4.1 Hardware Description
The interface between the S1D13708 and the MCF5307 requires no external glue logic.
The polarity of the WAIT# signal must be selected as active high by connecting CNF5 to
IO V
DD
(see Table 4-1:, “Summary of Power-On/Reset Configuration Options,” on
page 14).
The following diagram shows a typical implementation of the MCF5307 to S1D13708
interface.
Figure 4-1: Typical Implementation of MCF5307 to S1D13708 Interface
MCF5307
S1D13708
A[16:0]
D[23:16]
CS4
TA
BWE1
BWE0
OE
BCLK0
AB[16:0]
DB[7:0]
CS#
WAIT#
WE1#
WE0#
RD/WR#
RD#
CLKI
RESET#
BS#
System RESET
Note:
When connecting the S1D13708 RESET# pin, the system designer should be aware of all
conditions that may reset the S1D13708 (e.g. CPU reset can be asserted during wake-up
from power-down modes, or during debug states).
M/R#
A17
IO V
DD
D[31:24]
DB[15:8]