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S1D13708 Hardware Functional Specification
X39A-A-001-02 Issue Date: 02/03/07
8.3.2 Clock Configuration Registers
bits 5-4 MCLK Divide Select Bits [1:0]
These bits determine the divide used to generate the Memory Clock (MCLK) from the Bus
Clock (BCLK).
bits 6-4 PCLK Divide Select Bits [1:0]
These bits determine the divide used to generate the Pixel Clock (PCLK) from the Pixel
Clock Source.
Memory Clock Configuration Register
REG[04h] Read/Write
n/a MCLK Divide Select Bits 1-0 n/a
7 6543 2 1 0
Table 8-2: MCLK Divide Selection
MCLK Divide Select Bits BCLK to MCLK Frequency Ratio
00 1:1
01 2:1
10 3:1
11 4:1
Pixel Clock Configuration Register
REG[05h] Read/Write
n/a PCLK Divide Select Bits 2-0 n/a PCLK Source Select Bits 1-0
76543 210
Table 8-3: PCLK Divide Selection
PCLK Divide Select Bits PCLK Source to PCLK Frequency Ratio
000 1:1
001 2:1
010 3:1
011 4:1
1XX 8:1
