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Epson Research and Development Page 49
Vancouver Design Center
Hardware Functional Specification S1D13708
Issue Date: 02/03/07 X39A-A-001-02
1. t15 is the delay from when data is placed on the bus until the data is latched into the write buffer.
Note
Minimum one software WAIT state is required.
Table 6-7: Hitachi SH-4 Interface Timing
Symbol Parameter Min Max Unit
f
CKIO
Clock frequency
66 MHz
T
CKIO
Clock period
1/f
CKIO
ns
t3
A[16:0], M/R#, RD/WR# setup to CKIO
1ns
t4
A[16:0], M/R#, RD/WR# hold from CSn#
0ns
t5
BS# setup
1ns
t6
BS# hold
5ns
t7
CSn# setup
1ns
t8
CSn# high setup to CKIO
2ns
t9a
RDY asserted for MCLK = BCLK (max. MCLK = 50MHz)
7T
CKIO
t9b
RDY asserted for MCLK = BCLK ÷ 2
14 T
CKIO
t9c
RDY asserted for MCLK = BCLK ÷ 3
16 T
CKIO
t9d
RDY asserted for MCLK = BCLK ÷ 4
23 T
CKIO
t10
Falling edge RD# to D[15:0] driven (read cycle)
49ns
t11
Falling edge CSn# to RDY# driven high
49ns
t12
CKIO to RDY# low
514ns
t13
CSn# high to RDY# high
512ns
t14
Falling edge CKIO to RDY# high impedance
410ns
t15
D[15:0] setup to 2
nd
CKIO after BS# (write cycle) (see note 1)
0ns
t16
D[15:0] hold (write cycle)
0ns
t17
RDY# falling edge to D[15:0] valid (read cycle)
2ns
t18
Rising edge RD# to D[15:0] high impedance (read cycle)
39ns