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Page 112 Epson Research and Development
Vancouver Design Center
S1D13708 Hardware Functional Specification
X39A-A-001-02 Issue Date: 02/03/07
7 Clocks
7.1 Clock Descriptions
7.1.1 BCLK
BCLK is an internal clock derived from CLKI or XTAL. CLKI is typically provided from
the host CPU bus clock. The source clock options for BCLK may be selected as in the
following table.
Note
1
The ÷ 3 and ÷ 4 options may not work properly with bus interfaces
which have short back-to-back cycle timing.
2
XTAL should only be used for BCLK when using the Indirect Interface.
7.1.2 MCLK
MCLK provides the internal clock required to access the embedded SRAM. The S1D13708
is designed with efficient power saving control for clocks (clocks are turned off when not
used); reducing the frequency of MCLK does not necessarily save more power.
Furthermore, reducing the MCLK frequency relative to the BCLK frequency increases the
CPU cycle latency and so reduces screen update performance. For a balance of power
saving and performance, MCLK should be configured to have a high enough frequency
setting to provide sufficient screen refresh as well as acceptable CPU cycle latency.
The source clock options for MCLK may be selected as in the following table.
Table 7-1: BCLK Clock Selection
Source Clock Options BCLK Selection
CLKI CNF[7:6] = 00, REG[CAh] bit 0 = 0
CLKI
÷
2 CNF[7:6] = 01, REG[CAh] bit 0 = 0
CLKI ÷
3
1
CNF[7:6] = 10, REG[CAh] bit 0 = 0
CLKI ÷
4
1
CNF[7:6] = 11, REG[CAh] bit 0 = 0
XTAL
2
CNF[7:6] = 00, REG[CAh] bit 0 = 1
XTAL
2
÷
2 CNF[7:6] = 01, REG[CAh] bit 0 = 1
XTAL
2
÷
3
1
CNF[7:6] = 10, REG[CAh] bit 0 = 1
XTAL
2
÷
4
1
CNF[7:6] = 11, REG[CAh] bit 0 = 1