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Page 130 Epson Research and Development
Vancouver Design Center
S1D13708 Hardware Functional Specification
X39A-A-001-02 Issue Date: 02/03/07
bits 9-0 Vertical Display Period Start Position Bits [9:0]
These bits specify the Vertical Display Period Start Position for HR-TFT and D-TFD
panels in 1 line resolution.
Note
For passive LCD and TFT (non-HR-TFT/D-TFD) panels these bits must be set to 00h.
Note
This register must be programmed such that the following formula is valid.
VDPS + VDP < VT
Note
For panel AC timing and timing parameter definitions, see Section 6.4, “Display Inter-
face” on page 68.
bit 7 FPLINE Pulse Polarity
This bit selects the polarity of the horizontal sync signal. For most passive panels this bit
should be set to 1. For TFT panels this bit is set according to the horizontal sync signal
required by the panel, typically FPLINE or LP, depending on the panel type.
When this bit = 0, the horizontal sync signal is active low.
When this bit = 1, the horizontal sync signal is active high.
bits 6-0 FPLINE Pulse Width Bits [6:0]
These bits specify the width of the panel horizontal sync signal, in 1 pixel resolution. The
horizontal sync signal is typically FPLINE or LP, depending on the panel type.
FPLINE Pulse Width in number of pixels = (REG[20h] bits 6:0) + 1
Note
For panel AC timing and timing parameter definitions, see Section 6.4, “Display Inter-
face” on page 68.
Vertical Display Period Start Position Register 0
REG[1Eh] Read/Write
Vertical Display Period Start Position Bits 7-0
76543210
Vertical Display Period Start Position Register 1
REG[1Fh] Read/Write
n/a
Vertical Display Period Start
Position Bits 9-8
7 6 5 4 3 210
FPLINE Pulse Width Register
REG[20h] Read/Write
FPLINE Pulse
Polarity
FPLINE Pulse Width Bits 6-0
76543210