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S1D13708 Hardware Functional Specification
X39A-A-001-02 Issue Date: 02/03/07
6.4.5 Single Color 8-Bit Panel Timing (Format 1)
Figure 6-23 Single Color 8-Bit Panel Timing (Format 1)
VDP = Vertical Display Period
= (REG[1Dh] bits 1:0, REG[1Ch] bits 7:0) + 1 Lines
VNDP = Vertical Non-Display Period
= VT - VDP
= (REG[19h] bits 1:0, REG[18h] bits 7:0) - (REG[1Dh] bits 1:0, REG[1Ch] bits 7:0) Lines
HDP = Horizontal Display Period
= ((REG[14h] bits 6:0) + 1) x 8Ts
HNDP = Horizontal Non-Display Period
= HT - HDP
= (((REG[12h] bits 6:0) + 1) x 8Ts) - (((REG[14h] bits 6:0) + 1) x 8Ts)
FPLINE
FPSHIFT2
FPFRAME
FPLINE
FPSHIFT
FPDAT[7:0]
VDP
LINE1 LINE2 LINE3 LINE4
LINE239 LINE240
LINE1 LINE2
HDP
VNDP
HNDP
FPDAT5
FPDAT6
FPDAT4
FPDAT3
FPDAT2
FPDAT1
FPDAT0
FPDAT7
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
- Diagram drawn with 2 FPLINE vertical blank period
- Example timing for a 320x240 panel
Notes:
- Ts = Pixel clock period (PCLK)
- The duty cycle of FPSHIFT changes in order to process 16 pixels in 6 FPSHIFT/FPSHIFT2 rising edges
2Ts 2Ts
2Ts
2Ts 2Ts 2Ts 2Ts 2Ts 2Ts
2Ts 2Ts 2Ts 2Ts 2Ts
2Ts 2Ts 2Ts 2Ts 2Ts 2Ts
2Ts
4Ts
4Ts
4Ts 4Ts
4Ts4Ts
4Ts
4Ts
2Ts 2Ts 2Ts 2Ts 2Ts 2Ts
2Ts
1-R1
1-B1
1-G2
1-R3
1-B3
1-G4
1-R5
1-B5 1-R6
1-G5
1-B4
1-R4 1-R9 1-G9 1-G14 1-B14
1-R14
1-G13
1-B12
1-R121-B61-G6
1-R7
1-B7
1-G8
1-B9
1-G10
1-R11 1-G11 1-B16
1-B10
1-R10
1-B8
1-R8
1-G7
1-B11
1-B2
1-R2
1-G1
1-G3
1-R15
1-B15
1-G16
1-B13
1-G15
1-R13
1-G12
1-R16
1-
R316
1-
R316
1-
B316
1-
G317
1-
R318
1-
B318
1-
G319
1-
R320
1-
B320