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Epson Research and Development Page 27
Vancouver Design Center
Hardware Functional Specification S1D13708
Issue Date: 02/03/07 X39A-A-001-02
4 Pins
4.1 Pinout Diagram - PFBGA - 120pin
Figure 4-1 Pinout Diagram - PFBGA 120-pin
Table 4-1: PFBGA 120-pin Mapping
L
COREVDD IOVDD AB6 AB2 DB7 DB4 DB0 WAIT# FPLINE GPIO5 IOVDD
K
AB7 AB5 AB4 AB3 COREVDD DB3 M/R# IOVDD GPIO6 GPIO4 COREVDD
J
AB10 AB9 AB8 AB1 DB6 DB2 BS# FPFRAME GPIO1 GPIO2 GPIO3
H
AB14 AB13 AB11 AB0 DB5 DB1 RD# COREVDD PWMOUT GPIO0 DRDY
G
XTAL0 IOVDD AB15 AB12 VSS VSS VSS GPO6 CLKI2 FPSHIFT CVOUT
F
COREVDD CLKI XTAL1 AB16 VSS VSS GPO2 GPO5 GPO7 IOVDD
E
DB11 DB10 DB8 VSS VSS VSS VSS CNF7 GPO1 GPO3 GPO4
D
DB15 DB14 DB12 DB9 FPDAT0 FPDAT6 FPDAT12 FPDAT16 CNF6 TESTEN GPO0
C
WE0# CS# DB13 FPDAT1 FPDAT4 FPDAT7 IOVDD FPDAT13 FPDAT17 CNF4 CNF5
B
COREVDD WE1# RD/WR# FPDAT2 COREVDD FPDAT8 FPDAT10 FPDAT14 CNF0 CNF2 CNF3
A
IOVDD RESET# IOVDD FPDAT3 FPDAT5 FPDAT9 FPDAT11 FPDAT15 CNF1 COREVDD IOVDD
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L
K
J
H
G
F
E
D
C
B
A
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