Filter
Top Products
Epson Research and Development Page 65
Vancouver Design Center
Hardware Functional Specification S1D13708
Issue Date: 02/03/07 X39A-A-001-02
Note
Max frequency (f
BUSCLK
) when using crystal oscillator is 12MHz.
Table 6-15: Indirect Interface Timing (Mode 80)
Symbol Parameter Min Max Units
f
BUSCLK
Bus Clock frequency
50 MHz
T
BUSCLK
Bus Clock period
1/f
BUSCLK
ns
t3
A0 setup to (CS# | WRn#), (CS# | RDn#) falling edge
1ns
t4
A0 hold to (CS# | WRn#), (CS# | RDn#) rising edge
3ns
t5
D[15:0] setup to (CS# | WRn#) rising edge (write cycle)
1T
BUSCLK
t6
D[15:0] hold to (CS# | WRn#) rising edge (write cycle)
4ns
t7
Falling edge of (CS# | RDn#) to D[15:0] driven (read cycle)
2T
BUSCLK
t8a
Falling edge of (CS# | RDn#) to valid D[15:0] driven for MCLK = BCLK
(read cycle)
7.5 T
BUSCLK
t8b
Falling edge of (CS# | RDn#) to valid D[15:0] driven for MCLK = BCLK/2
(read cycle)
10.5 T
BUSCLK
t8c
Falling edge of (CS# | RDn#) to valid D[15:0] driven for MCLK = BCLK/3
(read cycle)
13.5 T
BUSCLK
t8d
Falling edge of (CS# | RDn#) to valid D[15:0] driven for MCLK = BCLK/4
(read cycle)
15.5 T
BUSCLK
t9
Valid D[15:0] hold to (CS# | RDn#) rising edge
0.5 T
BUSCLK
t10a
(CS# | WRn#) Low pulse width (write cycle)
4T
BUSCLK
t10b
(CS# | RDn#) Low pulse width for MCLK = BCLK (read cycle)
8T
BUSCLK
t10c
(CS# | RDn#) Low pulse width for MCLK = BCLK/2 (read cycle)
11 T
BUSCLK
t10d
(CS# | RDn#) Low pulse width for MCLK = BCLK/3 (read cycle)
15 T
BUSCLK
t10e
(CS# | RDn#) Low pulse width for MCLK = BCLK/4 (read cycle)
17 T
BUSCLK
t11a
(CS# | RDn#) High pulse width (read turnaround)
2T
BUSCLK
t11b
(CS# | WRn#) High pulse width for MCLK = BCLK (write turnaround)
2.5 T
BUSCLK
t11c
(CS# | WRn#) High pulse width for MCLK = BCLK/2 (write turnaround)
5.5 T
BUSCLK
t11d
(CS# | WRn#) High pulse width for MCLK = BCLK/3 (write turnaround)
7.5 T
BUSCLK
t11e
(CS# | WRn#) High pulse width for MCLK = BCLK/4 (write turnaround)
9.5 T
BUSCLK