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Epson Research and Development Page 13
Vancouver Design Center
Interfacing to the Intel StrongARM SA-1110 Microprocessor S1D13708
Issue Date: 01/11/25 X39A-G-019-01
4 StrongARM SA-1110 to S1D13708 Interface
4.1 Hardware Description
The SA-1110 microprocessor provides a variable latency I/O interface that can be used to
support an external LCD controller. By using the Generic # 2 Host Bus Interface, no glue
logic is required to interface the S1D13708 and the SA-1110.
A pull-up resistor is attached to WAIT# to speed up its rise time when terminating a cycle.
BS# (bus start) and RD/WR# are not used by the Generic #2 Host Bus Interface and must
be tied high (connected to IO V
DD
).
The following diagram shows a typical implementation of the SA-1110 to S1D13708
interface.
Figure 4-1: Typical Implementation of SA-1110 to S1D13708 Interface
WE1#
WE0#
DB[15:0]
WAIT#
RD#
CLKI
S1D13708
CS#
RESET#
AB[16:0]
nCAS1
nWE
D[15:0]
nCS4
nOE
SDCLK2
RDY
A[16:0]
SA-1110
Pull-up
BS#
RD/WR#
System RESET
Note:
When connecting the S1D13708 RESET# pin, the system designer should be aware of all
conditions that may reset the S1D13708 (e.g. CPU reset can be asserted during wake-up
from power-down modes, or during debug states).
IO V
DD
M/R#
A17
IO V
DD