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Epson Research and Development Page 51
Vancouver Design Center
Hardware Functional Specification S1D13708
Issue Date: 02/03/07 X39A-A-001-02
1. t14 is the delay from when data is placed on the bus until the data is latched into the write buffer.
Note
Minimum one software WAIT state is required.
Table 6-8: Hitachi SH-3 Interface Timing
Symbol Parameter Min Max Unit
f
CKIO
Bus Clock frequency
66 MHz
T
CKIO
Bus Clock period
1/f
CKIO
ns
t3
A[16:0], M/R#, RD/WR# setup to CKIO
1ns
t4
CSn# high setup to CKIO
1ns
t5
BS# setup
0ns
t6
BS# hold
5ns
t7
CSn# setup
1ns
t8
A[16:0], M/R#, RD/WR# hold from CS#
0ns
t9a
WAIT# asserted for MCLK = BCLK (max. MCLK = 50MHz)
6T
CKIO
t9b
WAIT# asserted for MCLK = BCLK ÷ 2
13 T
CKIO
t9c
WAIT# asserted for MCLK = BCLK ÷ 3
15 T
CKIO
t9d
WAIT# asserted for MCLK = BCLK ÷ 4
23 T
CKIO
t10
Falling edge RD# to D[15:0] driven (read cycle)
49ns
t11
Rising edge CSn# to WAIT# high impedance
37ns
t12
Falling edge CSn# to WAIT# driven low
411ns
t13
CKIO to WAIT# delay
514ns
t14
D[15:0] setup to 2
nd
CKIO after BS# (write cycle) (see note 1)
0ns
t15
D[15:0] hold (write cycle)
0ns
t16
WAIT# rising edge to D[15:0] valid (read cycle)
2ns
t17
Rising edge RD# to D[15:0] high impedance (read cycle)
39ns