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Epson Research and Development Page 151
Vancouver Design Center
Hardware Functional Specification S1D13708
Issue Date: 02/03/07 X39A-A-001-02
bit 3 and bit 0 CV Pulse Force High (bit 3) and CV Pulse Enable (bit 0)
These bits control the CVOUT pin and CV Pulse circuitry as follows.
When CVOUT is forced low or forced high it can be used as a general purpose output.
Note
Bit 0 must be set to 1 before initiating a new burst using the CV Pulse Burst Start bit.
Note
The CV Pulse circuitry is disabled when Power Save Mode is enabled.
bit 2 CV Pulse Burst Status
This is a read-only bit. A “1” indicates a CV pulse burst is occurring. A “0” indicates no
CV pulse burst is occurring. Software should wait for this bit to clear before starting
another burst.
bit 1 CV Pulse Burst Start
A 1 in this bit initiates a single CVOUT pulse burst. The number of clock pulses generated
is programmable from 1 to 256. The frequency of the pulses is the divided CV Pulse
source divided by 2, with 50/50 duty cycle. This bit should be cleared to 0 by software
before initiating a new burst.
Note
This bit has effect only if the CV Pulse Enable bit is 1.
bit 0 CV Pulse Enable
See description for bit 3.
Table 8-16: CV Pulse Control
Bit 3 Bit 0 Result
01
CV Pulse circuitry enabled
(controlled by REG[B1h] and REG[B2h])
0 0 CVOUT forced low
1 x CVOUT forced high
x = don’t care