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Page 162 Epson Research and Development
Vancouver Design Center
S1D13708 Hardware Functional Specification
X39A-A-001-02 Issue Date: 02/03/07
bit 1 PCLK1 Control
If the TFT Type 3 interface is selected (REG[C5h] bits 1-0 = 10), this bit enables the LCD
signal PCLK1.
When this bit = 1, PCLK1 = 1.
When this bit = 0, PCLK1 = 0.
bits 7-0 OE Rising Edge Position Bits [7:0]
These bits specify the rising edge position of the OE signal in 2 pixel resolution. This reg-
ister is used for the TFT Type 3 Interface and has no effect for all other panel interfaces.
bits 7-0 OE Pulse Width Bits [7:0]
These bits specify the pulse width of the OE signal in 2 pixel resolution. This register is
used for the TFT Type 3 Interface and has no effect for all other panel interfaces.
bits 7-0 POL Toggle Position Bits [7:0]
These bits specify the toggle position of the POL signal in 2 pixel resolution. This register
is used for the TFT Type 3 Interface and has no effect for all other panel interfaces.
bits 7-0 VCOM Toggle Position Bits [7:0]
These bits specify the toggle position of the VCOM signal in 2 pixel resolution. This reg-
ister is used for the TFT Type 3 Interface and has no effect for all other panel interfaces.
TFT Type 3 OE Rising Edge Position Register
REG[D5h] Read/Write
OE Rising Edge Position bits 7-0
76543210
TFT Type 3 OE Pulse Width Register
REG[D6h] Read/Write
OE Pulse Width bits 7-0
76543210
TFT Type 3 POL Toggle Position Register
REG[D7h] Read/Write
POL Toggle Position bits 7-0
76543210
TFT Type 3 VCOM Toggle Position Register
REG[D8h] Read/Write
VCOM Toggle Position bits 7-0
76543210