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Epson Research and Development Page 207
Vancouver Design Center
Hardware Functional Specification S1D13708
Issue Date: 02/03/07 X39A-A-001-02
The following shows an example of a “memory write” for Mode 80 when the Memory
Access Select bit is enabled (REG[C6h] bit 0 = 1).
Figure 15-11 Sample timing of “memory write” for Mode 80 when Memory Access Select Enabled
1. write register address of Memory Access Start register (REG[C4h]) (command write).
Note
No “data write” is required after a command write to the memory Access Start register
(REG[C4h]). This step configures the S1D13708 for burst memory access beginning
with the next data write.
2. write Memory data (data write).
If the Memory Access Select bit (REG[C6h] bit 0 = 1), memory accesses are word ac-
cesses even if WRU# is high (WRU# is ignored and WRL# is used to write both the
A0
CS#
WRU#
WRL#
RDU#
RDL#
D[7:0]
D[15:8]
DATA2DATA0 DATA8
DATA12
command write
MemoryAccessStart
data write data write data write data write
word access
DATA9
Little Endian
DATA n+1
DATA n
Big Endian
D[7:0]
D[15:8]
data write data write
data write
DATA4
DATA6
DATA10
DATA11
DATA n
DATA n+1
Little Endian
Data arrangement
word access
DATA1 DATA3 DATA5 DATA7
DATA13
word access
word access word access
word access
word access
Address +2
(word)
Address +2
(word)
Address +2
(word)
Address +2
(word)
Address +2
(word)
Address +2
(word)
1 2 2 2 2 22 2
STEP