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Page 16 Epson Research and Development
Vancouver Design Center
S1D13708 Hardware Functional Specification
X39A-A-001-02 Issue Date: 02/03/07
2 Features
2.1 Integrated Frame Buffer
• Embedded 80K byte SRAM display buffer.
2.2 CPU Interface
• Direct support of the following interfaces:
Generic MPU bus interface using WAIT# signal.
Hitachi SH-3.
Hitachi SH-4.
Motorola M68K.
Motorola MC68EZ328/MC68VZ328 DragonBall.
Motorola “REDCAP2” - no WAIT# signal.
Indirect Interface (Mode 68/Mode 80).
• 8-bit processor support with “glue logic”.
• “Fixed” low-latency CPU access times.
• Registers are memory-mapped - M/R# input selects between memory and register
address space.
• The complete 80K byte display buffer is directly and contiguously available through the
17-bit address bus.
• Single level CPU write buffer.
2.3 Display Support
• 4/8-bit monochrome LCD interface.
• 4/8/16-bit color LCD interface.
• Single-panel, single-drive passive displays.
• 9/12/18-bit Active Matrix TFT interface.
• Direct support for 18-bit Epson D-TFD interface.
• Direct support for 18-bit Sharp HR-TFT interface.
• Direct support for 18-bit Type 2, 3, and 4 TFT interfaces.