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Epson Research and Development Page 93
Vancouver Design Center
Hardware Functional Specification S1D13708
Issue Date: 02/03/07 X39A-A-001-02
1. Ts = pixel clock period
2. t1typ = (REG[23h] bits 1-0, REG[22h] bits 7-0) + 1
3. t2typ = ((REG[12h] bits 6-0) + 1) x 8
4. t3typ = (REG[20h] bits 6-0) + 1
5. t7typ = ((REG[17h] bits 1-0, REG[16h] bits 7-0) + 5) - ((REG[23h] bits 1-0, REG[22h] bits 7-0) + 1)
6. t8typ = ((REG[14h] bits 6-0) + 1) x 8
Figure 6-35 320x240 Sharp ‘Direct’ HR-TFT Panel Vertical Timing
Table 6-28: 320x240 Sharp ‘Direct’ HR-TFT Panel Horizontal Timing
Symbol Parameter Min Typ Max Units
t1
FPLINE start position 14 (note 2) Ts (note 1)
t2
Horizontal total period 400 note 3 440 Ts
t3
FPLINE width 1 (note 4) Ts
t4
FPSHIFT period 1 Ts
t5 Data setup to FPSHIFT rising edge 0.5 Ts
t6 Data hold from FPSHIFT rising edge 0.5 Ts
t7
Horizontal display start position 60 (note 5) Ts
t8
Horizontal display period 320 (note 6) Ts
t9
FPLINE rising edge to GPIO3 rising edge 59 Ts
t10 GPIO3 pulse width 1 Ts
t11 GPIO1, GPIO0 pulse width 353 Ts
t12 GPIO1 rising edge (GPIO0 falling edge) to FPLINE rise edge 5 Ts
t13 GPIO2 toggle edge to FPLINE rise edge 11 Ts
Table 6-29: 320x240 Sharp ‘Direct’ HR-TFT Panel Vertical Timing
Symbol Parameter Min Typ Max Units
t1
Vertical total period 245 330 Lines
t2
Vertical display start position 4 Lines
t3
Vertical display period 240 Lines
t4
Vertical sync pulse width 2 Lines
t1
t4
FPFRAME
t2 t3
LINE1
LINE2
LINE240
FPDAT[17:0]
(SPS)