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Epson Research and Development Page 15
Vancouver Design Center
Interfacing to the Motorola MCF5307 "ColdFire" Microprocessor S1D13708
Issue Date: 01/11/25 X39A-G-010-01
4.3 Register/Memory Mapping
The S1D13708 uses two 128K byte blocks which are selected using A17 from the
MCF5307 (A17 is connected to the S1D13708 M/R# pin). The internal registers occupy the
first 128K bytes block and the 80K byte display buffer occupies the second 128K byte
block. These two blocks of memory are aliased over the entire 2M byte space.
Note
If aliasing is not desirable, the upper addresses must be fully decoded.
4.4 MCF5307 Chip Select Configuration
Chip Selects 0 and 1 have programmable block sizes from 64K bytes through 2G bytes.
However, these chip selects would normally be needed to control system RAM and ROM.
Therefore, one of the IO chip selects CS2 through CS7 is required to address the entire
address space of the S1D13708. These IO chip selects have a fixed, 2M byte block size. In
the example interface, chip select 4 is used to control the S1D13708. The CSBAR register
should be set to the upper 8 bits of the desired base address.
The following options should be selected in the chip select mask registers (CSMR4/5).
• WP = 0 – disable write protect
• AM = 0 - enable alternate bus master access to the S1D13708
• C/I = 1 - disable CPU space access to the S1D13708
• SC = 1 - disable Supervisor Code space access to the S1D13708
• SD = 0 - enable Supervisor Data space access to the S1D13708
• UC = 1 - disable User Code space access to the S1D13708
• UD = 0 - enable User Data space access to the S1D13708
• V = 1 - global enable (“Valid”) for the chip select
The following options should be selected in the chip select control registers (CSCR4/5).
• WS0-3 = 0 - no internal wait state setting
• AA = 0 - no automatic acknowledgment
• PS (1:0) = 1:0 – memory port size is 16 bits
• BEM = 0 – Byte enable/write enable active on writes only
• BSTR = 0 – disable burst reads
• BSTW = 0 – disable burst writes