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Page 172 Epson Research and Development
Vancouver Design Center
S1D13708 Hardware Functional Specification
X39A-A-001-02 Issue Date: 02/03/07
10 Display Data Formats
The following diagrams show the display mode data formats for a little-endian system.
Figure 10-1 4/8/16 Bit-Per-Pixel Display Data Memory Organization
Note
1. The Host-to-Display mapping shown here is for a little endian system.
2. For 16 bpp format, R
n
, G
n
, B
n
represent the red, green, and blue color components.
4 bpp:
A
0
B
0
C
0
D
0
A
1
B
1
C
1
D
1
Host Address
Display Memory
A
2
B
2
C
2
D
2
A
3
B
3
C
3
D
3
bit 7 bit 0
A
4
B
4
C
4
D
4
A
5
B
5
C
5
D
5
Host Address
Display Memory
bit 7 bit 0
8 bpp:
A
0
B
0
C
0
D
0
E
0
F
0
G
0
H
0
A
1
B
1
C
1
D
1
E
1
F
1
G
1
H
1
A
2
B
2
C
2
D
2
E
2
F
2
G
2
H
2
Byte 0
Byte 1
Byte 2
Byte 0
Byte 1
Byte 2
Panel Display
P
0
P
1
P
2
P
3
P
4
P
5
P
6
P
7
Panel Display
P
0
P
1
P
2
P
3
P
4
P
5
P
6
P
7
(A
n
, B
n
, C
n
, D
n
, E
n
, F
n
, G
n
, H
n
)
16 bpp:
R
0
4
Host Address
Display Buffer
bit 7 bit 0
R
0
3
R
0
2
R
0
1
R
0
0
G
0
5
G
0
4
G
0
3
G
0
2
G
0
1
G
0
0
B
0
4
B
0
3
B
0
2
B
0
1
B
0
0
R
1
4
R
1
3
R
1
2
R
1
1
R
1
0
G
1
5
G
1
4
G
1
3
G
1
2
G
1
1
G
1
0
B
1
4
B
1
3
B
1
2
B
1
1
B
1
0
5-6-5 RGB
Byte 0
Byte 1
Byte 2
Byte 3
Panel Display
P
0
P
1
P
2
P
3
P
4
P
5
P
6
P
7
P
n
= (R
n
4-0
, G
n
5-0
, B
n
4-0
)
2 bpp:
A
0
B
0
A
1
B
1
A
2
B
2
A
3
B
3
Host Address
Display Memory
A
4
B
4
A
5
B
5
A
6
B
6
A
7
B
7
bit 7 bit 0
A
8
B
8
A
9
B
9
A
10
B
10
A
11
B
11
Byte 0
Byte 1
Byte 2
Panel Display
P
0
P
1
P
2
P
3
P
4
P
5
P
6
P
7
1 bpp:
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
Host Address
Display Memory
A
8
A
9
A
10
A
11
A
12
A
13
A
14
A
15
bit 7 bit 0
A
16
A
17
A
18
A
19
A
20
A
21
A
22
A
23
Byte 0
Byte 1
Byte 2
Panel Display
P
0
P
1
P
2
P
3
P
4
P
5
P
6
P
7
LUT
LUT
LUT
LUT
Bypasses LUT
P
n
= RGB value from LUT
Index (A
n
, B
n
, C
n
, D
n
)
P
n
= RGB value from LUT
Index (A
n
, B
n
)
P
n
= RGB value from LUT
Index (A
n
)
P
n
= RGB value from LUT Index