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Page 180 Epson Research and Development
Vancouver Design Center
S1D13708 Hardware Functional Specification
X39A-A-001-02 Issue Date: 02/03/07
12.2.1 Register Programming
Enable
90°
SwivelView™ Mode
Set SwivelView™ Mode Select bits to 01.
Display Start Address
The display refresh circuitry starts at pixel “B”, therefore the Display Start Address register
must be programmed with the address of pixel “B”. The example in the figure shows a 320-
pixel wide display, and if we assume 8-bpp display mode, the Display Start Address will
be 4Fh (the Display Start Address register is 0-based and in 32-bit increment).
Memory Address Offset
The Memory Address Offset register should be normally set to be the same as the display
width, e.g. 320 pixels or 50h (the Memory Address Offset register is in 32-bit increment).
This value may be increased to create a virtual display.
Panning
Panning is achieved by changing the Display Start Address register:
• Increment/decrement the Display Start Address register pans the display window
right/left by 32 bits, e.g. 4 pixels in 8-bpp mode.
• Increase/decrease the Display Start Address register by an amount equals to the Memory
Address Offset pans the display window down/up by 1 line.