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Page 14 Epson Research and Development
Vancouver Design Center
S1D13708 Connecting to a Micro-Controller via the Indirect Interface
X39A-G-020-01 Issue Date: 01/12/12
4.2 S1D13708 Hardware Configuration
The S1D13708 uses CNF7 through CNF0 to allow selection of the bus mode and other
configuration data on the rising edge of RESET#. For details on configuration, refer to the
S1D13708 Hardware Functional Specification, document number X39A-A-001-xx.
The following table shows the configuration required for this implementation of the
S1D13708 with the Indirect Interface. To select Mode 68, the BS# and RD# pins are tied
to V
SS
. To select Mode 80, only the BS# pin is tied to V
DD
.
Table 4-1: Summary of Power-On/Reset Configuration Options
S1D13708
Pin Name
value on this pin at the rising edge of RESET# is used to configure: (1/0)
10
CNF[4, 2:0]
0111 = Indirect Mode Little Endian Host Bus Interface
CNF3 GPIO pins as inputs at power on GPIO pins as HR-TFT / D-TFT outputs
CNF5
Active high WAIT# Active low WAIT#
CNF[7:6] See Table 4-2: “CLKI to BCLK Divide Selection” for recommended setting
= configuration for generic 8-bit processor
Table 4-2: CLKI to BCLK Divide Selection
CNF7 CNF6 CLKI to BCLK Divide
0 0 1:1
012:1
103:1
114:1
= recommended setting for Indirect Mode