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Page 72 Epson Research and Development
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S1D13708 Hardware Functional Specification
X39A-A-001-02 Issue Date: 02/03/07
6.4.2 Single Monochrome 4-Bit Panel Timing
Figure 6-17 Single Monochrome 4-Bit Panel Timing
VDP = Vertical Display Period
= (REG[1Dh] bits 1:0, REG[1Ch] bits 7:0) + 1 Lines
VNDP = Vertical Non-Display Period
= VT - VDP
= (REG[19h] bits 1:0, REG[18h] bits 7:0) - (REG[1Dh] bits 1:0, REG[1Ch] bits 7:0) Lines
HDP = Horizontal Display Period
= ((REG[14h] bits 6:0) + 1) x 8Ts
HNDP = Horizontal Non-Display Period
= HT - HDP
= (((REG[12h] bits 6:0) + 1) x 8Ts) - (((REG[14h] bits 6:0) + 1) x 8Ts)
FPLINE
FPSHIFT
FPFRAME
FPLINE
DRDY (MOD)
DRDY (MOD)
* Diagram drawn with 2 FPLINE vertical blank period
Example timing for a 320x240 panel
FPDAT[7:4]
FPDAT6
FPDAT5
FPDAT4
FPDAT7
VDP
LINE1 LINE2 LINE3 LINE4 LINE239 LINE240 LINE1 LINE2
1-2 1-6 1-318
1-3
1-7
1-319
1-4 1-8
1-320
1-1 1-5
1-317
VNDP
HDP
HNDP
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid