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S1D13708 Register Summary X39A-R-001-01
Pa
g
e 3 01/01/25
3 REG[05h] Pixel Clock Configuration Register
4 REG[05h] Pixel Clock Configuration Register
5 REG[10h] Panel Type Register
6 REG[10h] Panel Type Register
7 REG[70h] Display Mode Register
8 REG[71h] Special Effects Register
9 REG[B1h] PWM Clock / CV Pulse Configuration Register
10 REG[B1h] PWM Clock / CV Pulse Configuration Register
11 REG[B3h] PWMOUT Duty Cycle Register
PCLK Divide Select Bits PCLK Source to PCLK Frequency Ratio
000 1:1
001 2:1
010 3:1
011 4:1
1XX 8:1
PCLK Source Select Bits PCLK Source
00 MCLK
01 BCLK
10 CLKI
11 CLKI2
Panel Data Width Bits [1:0]
Passive LCD Panel Data Width
Size
Active Panel Data Width Size
00 4-bit 9-bit
01 8-bit 12-bit
10 16-bit 18-bit
11 Reserved Reserved
REG[10h] Bits[1:0] Panel Type
00 STN
01 TFT
10 HR-TFT
11 D-TFD
Bit-per-pixel
Select Bits [1:0]
Color Depth (bpp)
Maximum Number of Colors/Shades Max. No. Of
Simultaneously
Displayed Colors/
Shades
Passive Panel
(Dithering On)
TFT Panel
000 1 bpp 256K/64 256K/64 2/2
001 2 bpp 256K/64 256K/64 4/4
010 4 bpp 256K/64 256K/64 16/16
011 8 bpp 256K/64 256K/64 256/64
100 16 bpp 64K/64 64K/64 64K/64
101, 110, 111 Reserved n/a n/a n/a
SwivelView
TM
Mode Select Bits SwivelView
TM
Orientation
00 Normal
01 90°
10 180°
11 270°
PWM Clock Divide Select Bits [3:0] PWM Clock Divide Amount
0h 1
1h 2
2h 4
3h 8
... ...
Ch 4096
Dh-Fh Reserved
CV Pulse Divide Select Bits [2:0] CV Pulse Divide Amount
0h 1
1h 2
2h 4
3h 8
... ...
7h 128
PWMOUT Duty Cycle [7:0] PWMOUT Duty Cycle
00h Always Low
01h High for 1 out of 256 clock periods
02h High for 2 out of 256 clock periods
... ...
FFh High for 255 out of 256 clock periods