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Epson Research and Development Page 59
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Hardware Functional Specification S1D13708
Issue Date: 02/03/07 X39A-A-001-02
1. t12 is the delay from when data is placed on the bus until the data is latched into the write buffer.
Table 6-12: Motorola DragonBall Interface with DTACK Timing
Symbol Parameter
MC68EZ328 MC68VZ328
Unit
Min Max Min Max
f
CLKO
Bus Clock frequency 16 33 MHz
T
CLKO
Bus Clock period
1/f
CLKO
1/f
CLKO
ns
t3
A[16:0] setup 1st CLKO when CSX = 0 and either UWE/LWE
or OE
= 0
00 ns
t4 A[16:0] hold from CSX rising edge 0 0 ns
t5a DTACK asserted for MCLK = BCLK 8 8 T
CLKO
t5b DTACK asserted for MCLK = BCLK ÷ 21313T
CLKO
t5c DTACK asserted for MCLK = BCLK ÷ 31616T
CLKO
t5d DTACK asserted for MCLK = BCLK ÷ 42222T
CLKO
t6 CSX setup to CLKO rising edge 2 2 ns
t7 CSX rising edge to CLKO rising edge 2 2 ns
t8 UWE/LWE falling edge to CLKO rising edge 2 2 ns
t9 UWE
/LWE rising edge to CSX rising edge 0 0 ns
t10 OE falling edge to CLKO rising edge 2 2 ns
t11 OE hold from CSX rising edge 0 0 ns
t12
D[15:0] setup to 3rd CLKO when CSX
, UWE/LWE asserted
(write cycle) (see note 1)
01 ns
t13 D[15:0] in hold from CSX
rising edge (write cycle) 0 0 ns
t14 Falling edge of OE
to D[15:0] driven (read cycle) 4 10 4 10 ns
t15 CSX rising edge to D[15:0] output Hi-Z (read cycle) 3939 ns
t16 CSX falling edge to DTACK driven high 4 9 4 10 ns
t17 DTACK
falling edge to D[15:0] valid (read cycle) 0 0 ns
t18 CSX high to DTACK high 513514 ns
t19 CLKO rising edge to DTACK Hi-Z 49410 ns