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Page 168 Epson Research and Development
Vancouver Design Center
S1D13708 Hardware Functional Specification
X39A-A-001-02 Issue Date: 02/03/07
bits 5-0 Partial Area 2 X Start Position Bits [5:0]
These bits specify the X Start Position of Partial Area 2 in 8 pixel resolution. This register
is used for the TFT Type 3 Interface and has no effect for all other panel interfaces.
bits 5-0 Partial Area 2 Y Start Position Bits [5:0]
These bits specify the Y Start Position of Partial Area 2 in 8 line resolution. This register is
used for the TFT Type 3Interface and has no effect for all other panel interfaces.
bits 5-0 Partial Area 2 X End Position Bits [5:0]
These bits specify the X End Position of Partial Area 2 in 8 pixel resolution. This register
is used for the TFT Type 3 Interface and has no effect for all other panel interfaces.
bits 5-0 Partial Area 2 Y End Position Bits [5:0]
These bits specify the Y End Position of Partial Area 2 in 8 line resolution. This register is
used for the TFT Type 3 Interface and has no effect for all other panel interfaces.
TFT Type 3 Partial Area 2 X Start Position Register
REG[EAh] Read/Write
n/a Partial Area 2 X Start Position bits 5-0
7 6543210
TFT Type 3 Partial Area 2 Y Start Position Register
REG[EBh] Read/Write
n/a Partial Area 2 Y Start Position bits 5-0
7 6543210
TFT Type 3 Partial Area 2 X End Position Register
REG[ECh] Read/Write
n/a Partial Area 2 X End Position bits 5-0
7 6543210
TFT Type 3 Partial Area 2 Y End Position Register
REG[EDh] Read/Write
n/a Partial Area 2 Y End Position bits 5-0
7 6543210