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Epson Research and Development Page 7
Vancouver Design Center
13708CFG Configuration Program S1D13708
Issue Date: 01/11/16 X39A-B-001-01
Note
When “Epson S5U13708B00B” is selected, the register and display buffer addresses are
blanked because the evaluation board uses the PCI interface and the decode addresses
are determined by the system BIOS during boot-up.
When “Epson Evaluation Board” is selected, the register and display buffer addresses
are blanked because the evaluation board communicates via the serial port.
Register Address The physical address of the start of register decode
space (in hexadecimal).
This field is automatically set according to the Decode
Address unless the “User-Defined” decode address is
selected.
Display Buffer Address The physical address of the start of display buffer
decode space (in hexadecimal).
This field is automatically set according to the Decode
Address unless the “User-Defined” decode address is
selected.
Indirect Interface This setting selects software support for the S1D13708
Indirect Bus Interface.
Clock Chip Support The S5U13708B00B evaluation board implements a
Cypress ICD2061A Clock Synthesizer which can be
used to generate CLKI and CLKI2. When this box is
checked, GPIO[3:1] are reserved for Clock Synthesizer
support. Selecting a HR-TFT panel will disable this
feature as the HR-TFT requires GPIO[3:0]. Note that
this feature is only available when using the
S5U13708B00B.