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Page 120 Epson Research and Development
Vancouver Design Center
S1D13708 Hardware Functional Specification
X39A-A-001-02 Issue Date: 02/03/07
General Purpose IO Pins Registers
REG[A8h] General Purpose IO Pins Configuration Register 0 145 REG[A9h] General Purpose IO Pins Configuration Register 1 146
REG[ACh] General Purpose IO Pins Status/Control Register 0 146 REG[ADh] General Purpose IO Pins Status/Control Register 1 149
PWM Clock and CV Pulse Configuration Registers
REG[B0h] PWM Clock / CV Pulse Control Register 150 REG[B1h] PWM Clock / CV Pulse Configuration Register 152
REG[B2h] CV Pulse Burst Length Register 153 REG[B3h] PWMOUT Duty Cycle Register 153
Extended Registers
REG[C0h] Memory Access Pointer 0 154 REG[C1h] Memory Access Pointer 1 154
REG[C2h] Memory Access Pointer 2 154 REG[C4h] Memory Access Start 154
REG[C5h] Extended Panel Type Register 155 REG[C6h] Memory Access Select Register 155
REG[C7h] Ink Layer Transparent Color Register 0 156 REG[C8h] Ink Layer Transparent Color Register 1 156
REG[C9h] Ink Layer Register 157 REG[CAh] BCLK Source Select Register 157
REG[CBh] Data Compare Invert Enable Register 158
REG[D0h] TFT Type 2 VCLK Configuration Register 159 REG[D1h] TFT Type 2 AP Configuration Register 160
REG[D4h] TFT Type 3 Control Signal Enable Register 161 REG[D5h] TFT Type 3 OE Rising Edge Position Register 162
REG[D6h] TFT Type 3 OE Pulse Width Register 162 REG[D7h] TFT Type 3 POL Toggle Position Register 162
REG[D8h] TFT Type 3 VCOM Toggle Position Register 162 REG[D9h] TFT Type 3 CPV Pulse Width Register 163
REG[DAh] TFT Type 3 XOEV Rising Edge Position Register 163 REG[DBh] TFT Type 3 XOEV Falling Edge Position Register 163
REG[DCh] TFT Type 3 PCLK Divide Register 164 REG[E0h] TFT Type 3 Partial Mode Display Area Control Register 165
REG[E1h] TFT Type 3 Partial Mode Display Refresh Cycle Register165 REG[E2h] TFT Type 3 Partial Area 0 X Start Position Register 166
REG[E3h] TFT Type 3 Partial Area 0 Y Start Position Register 166 REG[E4h] TFT Type 3 Partial Area 0 X End Position Register 166
REG[E5h] TFT Type 3 Partial Area 0 Y End Position Register 166 REG[E6h] TFT Type 3 Partial Area 1 X Start Position Register 167
REG[E7h] TFT Type 3 Partial Area 1 Y Start Position Register 167 REG[E8h] TFT Type 3 Partial Area 1 X End Position Register 167
REG[E9h] TFT Type 3 Partial Area 1 Y End Position Register 167 REG[EAh] TFT Type 3 Partial Area 2 X Start Position Register 168
REG[EBh] TFT Type 3 TFT Partial Area 2 Y Start Position Register 168 REG[ECh] TFT Type 3 Partial Area 2 X End Position Register 168
REG[EDh] TFT Type 3 Partial Area 2 Y End Position Register 168 REG[F0h] TFT Type 3 Command 0 Store Register 0 169
REG[F1h] TFT Type 3 Command 0 Store Register 1 169 REG[F2h] TFT Type 3 Command 1 Store Register 0 169
REG[F3h] TFT Type 3 Command 1 Store Register 1 169 REG[F4h] TFT Type 3 Command Send Request Register 169
REG[F5h] TFT Type 3 Source Driver IC Number Register 170
Table 8-1: S1D13708 Register Set
Register Pg Register Pg