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Page 6 Epson Research and Development
Vancouver Design Center
S1D13708 13708CFG Configuration Program
X39A-B-001-01 Issue Date: 01/11/16
13708CFG Configuration Tabs
13708CFG provides a series of tabs which can be selected at the top of the main window.
Each tab allows the configuration of a specific aspect of S1D13708 operation. The
following sections describe the purpose and use of each of the tabs.
General Tab
The General tab contains settings that define the S1D13708 operating environment.
Decode Addresses Selecting one of the listed evaluation platforms changes
the values for the “Register address” and “Display
buffer address” fields. The values used for each evalu-
ation platform are examples of possible implementa-
tions as used by the Epson S1D13708 evaluation board.
If your hardware implementation differs from the
addresses used, select the User-Defined option and
enter the correct addresses for “Register address” and
“Display buffer address”.
Decode Addresses
Register Address
Display Buffer Address
Clock Chip Support
Indirect Interface