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Epson Research and Development Page 161
Vancouver Design Center
Hardware Functional Specification S1D13708
Issue Date: 02/03/07 X39A-A-001-02
Note
The GPO pins are used by the TFT Type 3 interface when REG[C5h] bits 1-0 = 10. For
pin mapping for TFT Type 3, see Table 4-10: “LCD Interface Pin Mapping,” on page
40.
bit 7 PDME Control
If the TFT Type 3 interface is selected (REG[C5h] bits 1-0 = 10), this bit controls the LCD
signal PDME.
When this bit = 1, PDME = 1.
When this bit = 0, PDME = 0.
bit 6 XSTBY Control
If the TFT Type 3 interface is selected (REG[C5h] bits 1-0 = 10), this bit controls the LCD
signal XSTBY.
When this bit = 1, XSTBY = 1.
When this bit = 0, XSTBY = 0.
bit 5 XOHV Control
If the TFT Type 3 interface is selected (REG[C5h] bits 1-0 = 10), this bit controls the LCD
signal XOHV.
When this bit = 1, XOHV = 1.
When this bit = 0, XOHV = 0.
bit 4 XRESV Control
If the TFT Type 3 interface is selected (REG[C5h] bits 1-0 = 10), this bit controls the LCD
signal XRESV.
When this bit = 1, XRESV = 1.
When this bit = 0, XRESV = 0.
bit 3 XRESH Control
If the TFT Type 3 interface is selected (REG[C5h] bits 1-0 = 10), this bit controls the LCD
signal XRESH.
When this bit = 1, XRESH = 1.
When this bit = 0, XRESH = 0.
bit 2 PCLK2 Control
If the TFT Type 3 interface is selected (REG[C5h] bits 1-0 = 10), this bit enables the LCD
signal PCLK2.
When this bit = 1, PCLK2 = 1.
When this bit = 0, PCLK2 = 0.
TFT Type 3 Signal Control Register
REG[D4h] Read/Write
PDME
Control
XSTBY
Control
XOHV Control
XRESV
Control
XRESH
Control
PCLK2
Enable
PCLK1
Enable
n/a
76543210