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Epson Research and Development Page 5
Vancouver Design Center
Interfacing to the Motorola MPC821 Microprocessor S1D13708
Issue Date: 01/11/06 X39A-G-009-01
List of Tables
Table 3-1: Host Bus Interface Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 4-1: List of Connections from MPC821ADS to S1D13708 . . . . . . . . . . . . . . . . . . 16
Table 4-2: Summary of Power-On/Reset Configuration Options . . . . . . . . . . . . . . . . . . . 18
Table 4-3: CLKI to BCLK Divide Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
List of Figures
Figure 2-1: Power PC Memory Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 2-2: Power PC Memory Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Figure 2-3: GPCM Memory Devices Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Figure 4-1: Typical Implementation of MPC821 to S1D13708 Interface . . . . . . . . . . . . . . .15