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Epson Research and Development Page 11
Vancouver Design Center
Interfacing to the Motorola RedCap2 S1D13708
Issue Date: 01/11/06 X39A-G-014-01
3.2 Host Bus Interface Signals
The Host Bus Interface requires the following signals:
• CLKI is a clock input which is required by the S1D13708 host bus interface and
connects to CKO of the REDCAP2.
• The address inputs AB[16:0], and the data bus DB[15:0], connect directly to the
REDCAP2 bus address (A[16:0]) and data bus (D[15:0]), respectively. CNF[2:0] and
CNF4 must be set to select the REDCAP2 host bus interface with big endian mode.
• M/R# (memory/register) selects between memory or register access. It may be
connected to an address line, allowing REDCAP2 bus address A17 to be connected to
the M/R# line.
• CS# (Chip Select) must be driven low whenever the S1D13708 is accessed by the
REDCAP2 bus.
• RD/WR# connects to R/W
which indicates whether a read or a write access is being
performed on the S1D13708.
• WE1# and WE0# connect to EB0
and EB1 (Enable Byte 0 and 1) for byte steering.
• RD# connects to OE
(Output Enable). This signal must be driven by the REDCAP2 bus
to indicate the bus access is a read and enables slave devices to drive the data bus with
read data.
• The BS# and WAIT# signals are not needed for this bus interface, they should be
connected to IO V
DD
.