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Epson Research and Development Page 53
Vancouver Design Center
Hardware Functional Specification S1D13708
Issue Date: 02/03/07 X39A-A-001-02
1. t17 is the delay from when data is placed on the bus until the data is latched into the write buffer.
Table 6-9: Motorola MC68K #1 Interface Timing
Symbol Parameter Min Max Unit
f
CLK
Bus Clock Frequency 50 MHz
T
CLK
Bus Clock period 1/f
CLK
ns
t3
A[16:1], R/W#, M/R# setup to first CLK rising edge where CS# = 0,
AS# = 0, UDS# = 0, and LDS# = 0
1ns
t4 A[16:1], M/R# hold from AS# rising edge 0 ns
t5 CS# setup to CLK rising edge while CS#, AS#, UDS#/LDS# = 0 1 ns
t6 CS# hold from AS# rising edge 0 ns
t7a DTACK# asserted for MCLK = BCLK 8 T
CLK
t7b DTACK# asserted for MCLK = BCLK ÷ 213T
CLK
t7c DTACK# asserted for MCLK = BCLK ÷ 317T
CLK
t7d DTACK# asserted for MCLK = BCLK
÷ 423T
CLK
t8 AS# setup to CLK rising edge while CS#, AS#, UDS#/LDS# = 0 1 ns
t9 AS# setup to CLK rising edge 1 ns
t10 UDS#/LDS# setup to CLK rising edge while CS#, AS#, UDS#/LDS# = 0 1 ns
t11 UDS#/LDS# high setup to CLK rising edge 1 ns
t12 First CLK rising edge where AS# = 1 to DTACK# high impedance 3 10 ns
t13 R/W# setup to CLK rising edge before all CS#, AS#, UDS# and/or LDS# = 0 1 ns
t15 AS# = 0 and CS# = 0 to DTACK# driven high 4 10 ns
t16 AS# rising edge to DTACK# rising edge 5 14 ns
t17
D[15:0] valid to third CLK rising edge where CS# = 0, AS# = 0 and either
UDS# = 0 or LDS# = 0 (write cycle) (see note 1)
1ns
t18 D[15:0] hold from DTACK# falling edge (write cycle) 0 ns
t19 UDS# = 0 and/or LDS# = 0 to D[15:0] driven (read cycle) 3 9 ns
t20 DTACK# falling edge to D[15:0] valid (read cycle) 0 ns
t21 UDS#, LDS# rising edge to D[15:0] high impedance (read cycle) 3 4 ns