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Epson Research and Development Page 47
Vancouver Design Center
Hardware Functional Specification S1D13708
Issue Date: 02/03/07 X39A-A-001-02
1. t11 is the delay from when data is placed on the bus until the data is latched into the write buffer.
Table 6-6: Generic #2 Interface Timing
Symbol Parameter Min Max Unit
f
BUSCLK
Bus Clock frequency 50 MHz
T
BUSCLK
Bus Clock period 1/f
BUSCLK
ns
t3
A[16:0], M/R#, BHE# setup to first BUSCLK rising edge where CS# = 0 and
either RD# = 0 or WE# = 0
1ns
t4 A[16:0], M/R#, BHE# hold from either RD# or WE# rising edge 0 ns
t5 CS# setup to BUSCLK rising edge 1 ns
t6 CS# hold from either RD# or WE# rising edge 0 ns
t7a WAIT# asserted for MCLK = BCLK 8 T
BUSCLK
t7b WAIT# asserted for MCLK = BCLK ÷ 213T
BUSCLK
t7c WAIT# asserted for MCLK = BCLK ÷ 315T
BUSCLK
t7d WAIT# asserted for MCLK = BCLK ÷ 421T
BUSCLK
t8 RD# or WE# setup to BUSCLK rising edge 1 ns
t9 Falling edge of either RD# or WE# to WAIT# driven low 5 12 ns
t10 Rising edge of either RD# or WE# to WAIT# high impedance 3 8 ns
t11
D[15:0] setup to third BUSCLK rising edge where CS# = 0 and WE# = 0
(write cycle) (see note 1)
1ns
t12 D[15:0] hold from WAIT# rising edge (write cycle) 0 ns
t13 RD# falling edge to D[15:0] driven (read cycle) 5 11 ns
t14 WAIT# rising edge to D[15:0] valid (read cycle) 2 ns
t15 Rising edge of RD# to D[15:0] high impedance (read cycle) 3 9 ns