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Page 160 Epson Research and Development
Vancouver Design Center
S1D13708 Hardware Functional Specification
X39A-A-001-02 Issue Date: 02/03/07
bit 7 POL Type
This bit selects how often the POL signal is toggled. The POL signal is used for the TFT
Type 2 Interface. For all other panel interfaces this bit has no effect.
When this bit = 0, the POL signal is toggled every line.
When this bit = 1, the POL signal is toggled every frame.
bits 5-3 AP Pulse Width Bits [2:0]
These bits specify the AP Pulse Width used for the TFT Type Interface. For all other panel
interfaces it has no effect.
bits 1-0 AP Rising Position Bits [1:0]
These bits control the TFT Type 2 AC timing parameter from the rising edge of STB to the
rising edge of AP. The parameter is selected as follows. For all other panel interfaces it has
no effect.
TFT Type 2 AP Configuration Register
REG[D1h] Read/Write
POL Type n/a AP Pulse Width bits 2-0 n/a AP Rising Position bits 1-0
7 6543210
Table 8-23: AP Pulse Width
REG[D1h] bits 5-3 AP Pulse Width (in PCLKs)
000 20
001 40
010 80
011 120
100 150
101 190
110 240
111 270
Table 8-24: AP Rising Position
REG[D1h] bits 1-0 GPIO1 (AP) Rising Position (in PCLKs)
00 40
01 52
10 68
11 90