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Page 12 Epson Research and Development
Vancouver Design Center
S1D13708 Interfacing to 8-bit Processors
X39A-G-015-01 Issue Date: 01/11/25
4.2 S1D13708 Hardware Configuration
The S1D13708 uses CNF7 through CNF0 to allow selection of the bus mode and other
configuration data on the rising edge of RESET#. For details on configuration, refer to the
S1D13708 Hardware Functional Specification, document number X39A-A-001-xx.
The following table shows the configuration required for this implementation of a
S1D13708 to generic 8-bit processor.
Table 4-2: CLKI to BCLK Divide Selection
4.3 Register/Memory Mapping
The S1D13708 is a memory mapped device. The S1D13708 uses two 128K byte blocks
which are selected using A17 from the 8-bit processor (A17 is connected to the S1D13708
M/R# pin). The internal registers occupy the first 128K byte block and the 80K byte display
buffer occupies the second 128K byte block.
An external decoder can be used to decode the address lines and generate a chip select for
the S1D13708 whenever the selected 128k byte memory block is accessed. If the processor
supports a general chip select module, its internal registers can be programmed to generate
a chip select for the S1D13708 whenever the S1D13708 memory block is accessed.
Table 4-1: Summary of Power-On/Reset Configuration Options
S1D13708
Pin Name
value on this pin at the rising edge of RESET# is used to configure: (1/0)
10
CNF[4, 2:0]
0100 = Generic #2 Little Endian Host Bus Interface
CNF3 GPIO pins as inputs at power on GPIO pins as HR-TFT / D-TFT outputs
CNF5
Active high WAIT# Active low WAIT#
CNF[7:6] see Table 4-2: “CLKI to BCLK Divide Selection” for recommended setting
= configuration for generic 8-bit processor
CNF7 CNF6 CLKI to BCLK Divide
0 0 1:1
012:1
103:1
114:1
= recommended setting for generic 8-bit processor