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Page 10 Epson Research and Development
Vancouver Design Center
S1D13708 13708CFG Configuration Program
X39A-B-001-01 Issue Date: 01/11/16
The S1D13708 may use one or two clock sources. Two clock sources allow greater flexi-
bility in display type and memory speed.
CLKI This setting determines the frequency of CLKI.
Timing Set this value by selecting a preset frequency from the
drop down list or entering the desired frequency (MHz)
in the edit box.
Actual This field displays the actual value of the CLKI
frequency. If “Enable clock chip support” is selected on
the General Tab, then this value may differ slightly
from the value entered in the timing control.
CLKI2 This setting determines the frequency of CLKI2.
Timing Set this value by selecting a preset frequency from the
drop down list or entering the desired frequency (MHz)
in the edit box.
Actual This field displays the actual value of the CLKI2
frequency. If “Enable clock chip support” is selected on
the General Tab, then this value may differ slightly
from the value entered in the timing control.
XTAL These settings select the clock frequency for the Crystal
Oscillator Input (XTAL).
Timing This field selects the actual XTAL frequency used by
the configuration process.
PCLK These settings select the clock signal source and divisor
for the pixel clock (PCLK).
Source Selects the PCLK source. Possible sources include
CLKI, CLKI2, BCLK, MCLK or XTAL. Note that
BCLK and MCLK may be previously divided from
CLKI or CLKI2.
Divide Specifies the divide ratio for the clock source. The
divide ratio is applied to the PCLK source to derive
PCLK.
Selecting “Auto” for the divisor allows the configu-
ration program to calculate the best clock divisor.
Unless a very specific clocking is being specified, it is
best to leave this setting on “Auto”.