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Page 18 Epson Research and Development
Vancouver Design Center
S1D13708 Interfacing to the Motorola MPC821 Microprocessor
X39A-G-009-01 Issue Date: 01/11/06
4.3 S1D13708 Hardware Configuration
The S1D13708 uses CNF7 through CNF0 to allow selection of the bus mode and other
configuration data on the rising edge of RESET#. For details on configuration, refer to the
S1D13708 Hardware Functional Specification, document number X39A-A-001-xx.
The following table shows the configuration required for this implementation of a
S1D13708 to Motorola MPC821 microprocessor.
Table 4-3: CLKI to BCLK Divide Selection
4.4 Register/Memory Mapping
The DRAM on the MPC821 ADS board extends from address 0 through 3F FFFFh, so the
S1D13708 is addressed starting at 40 0000h. The S1D13708 uses two 128K byte blocks
which are selected using A14 from the MPC821 (A14 is connected to the S1D13708 M/R#
pin). The internal registers occupy the first 128K bytes block and the 80K byte display
buffer occupies the second 128K byte block.
Table 4-2: Summary of Power-On/Reset Configuration Options
S1D13708 Pin
Name
value on this pin at the rising edge of RESET# is used to configure: (1/0)
10
CNF[4, 2:0]
1011 = Generic #1 Big Endian Host Bus Interface
CNF3 GPIO pins as inputs at power on GPIO pins as HR-TFT / D-TFT outputs
CNF5
Active high WAIT# Active low WAIT#
CNF[7:6] see Table 4-3: “CLKI to BCLK Divide Selection” for recommended settings
= configuration for MPC821 microprocessor
CNF7 CNF6 CLKI to BCLK Divide
0 0 1:1
012:1
103:1
114:1
= recommended setting for MPC821 microprocessor