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Page 212 Epson Research and Development
Vancouver Design Center
S1D13708 Hardware Functional Specification
X39A-A-001-02 Issue Date: 02/03/07
17 Big-Endian Bus Interface
17.1 Byte Swapping Bus Data
The display buffer and register architecture of the S1D13708 is inherently little-endian. If
configured as big-endian (CNF4 = 1 at reset), bus accesses are automatically handled by
byte swapping all read/write data to/from the internal display buffer and registers.
Bus data byte swapping translates all byte accesses correctly to the S1D13708 register and
display buffer locations. To maintain the correct translation for 16-bit word access, even
address bytes must be mapped to the MSB of the 16-bit word, and odd address bytes to the
LSB of the 16-bit word. For example:
Byte write 11h to register address 1Eh -> REG[1Eh] <= 11h
Byte write 22h to register address 1Fh -> REG[1Fh] <= 22h
Word write 1122h to register address 1Eh-> REG[1Eh] <= 11h
REG[1Fh] <= 22h