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Epson Research and Development Page 129
Vancouver Design Center
Hardware Functional Specification S1D13708
Issue Date: 02/03/07 X39A-A-001-02
bits 9-0 Vertical Total Bits [9:0]
These bits specify the LCD panel Vertical Total period, in 1 line resolution. The Vertical
Total is the sum of the Vertical Display Period and the Vertical Non-Display Period. The
maximum Vertical Total is 1024 lines.
Vertical Total in number of lines = (REG[18h] bits 7:0, REG[19h] bits 1:0) + 1
Note
1
This register must be programmed such that the following formula is valid.
VDPS + VDP < VT
2
For panel AC timing and timing parameter definitions, see Section 6.4, “Display Inter-
face” on page 68.
bits 9-0 Vertical Display Period Bits [9:0]
These bits specify the LCD panel Vertical Display period, in 1 line resolution. The Vertical
Display period should be less than the Vertical Total to allow for a sufficient Vertical
Non-Display period.
Vertical Display Period in number of lines = (REG[1Ch] bits 7:0, REG[1Dh] bits 1:0) + 1
Note
For panel AC timing and timing parameter definitions, see Section 6.4, “Display Inter-
face” on page 68.
Vertical Total Register 0
REG[18h] Read/Write
Vertical Total Bits 7-0
76543210
Vertical Total Register 1
REG[19h] Read/Write
n/a Vertical Total Bits 9-8
7 6 5 4 3 210
Vertical Display Period Register 0
REG[1Ch] Read/Write
Vertical Display Period Bits 7-0
76543210
Vertical Display Period Register 1
REG[1Dh] Read/Write
n/a
Vertical Display Period
Bits 9-8
7 6 5 4 3 210