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Page 10 Epson Research and Development
Vancouver Design Center
S1D13708 Interfacing to the Motorola MC68VZ328 Dragonball Microprocessor
X39A-G-016-01 Issue Date: 01/11/25
3.2 Host Bus Interface Signals
The Host Bus Interface requires the following signals.
• CLKI is a clock input required by the S1D13708 Host Bus Interface as a source for its
internal bus and memory clocks. This clock is typically driven by the host CPU system
clock. For this example, CLK0 from the Motorola MC68VZ328 is used for CLKI.
• The address inputs AB[16:0], and the data bus DB[15:0], connect directly to the
MC68VZ328 address (A[16:0]) and data bus (D[15:0]), respectively. CNF4 must be set
to one to select big endian mode.
• Chip Select (CS#) must be driven low by one of the Dragonball VZ chip select outputs
from the chip select module whenever the S1D13708 is accessed by the MC68VZ328.
• M/R# (memory/register) selects between memory or register accesses. This signal is
generated by the external address decode circuitry. For this example, M/R# may be
connected to an address line, allowing system address A17 to be connected to the M/R#
line.
• WE0# connects to LWE
(the low data byte write strobe enable of the MC68VZ328) and
is asserted when valid data is written to the low byte of a 16-bit device.
• WE1# connects to UWE
(the upper data byte write strobe enable of the MC68VZ328)
and is asserted when valid data is written to the high byte of a 16-bit device.
• RD# connects to OE
(the read output enable of the MC68VZ328) and is asserted during
a read cycle of the MC68VZ328 microprocessor.
• RD/WR# is not used for the Dragonball host bus interface and must be tied high to
IO V
DD
.
• WAIT# connects to D
TACK and is a signal which is output from the S1D13708 indi-
cating the MC68VZ328 must wait until data is ready (read cycle) or accepted (write
cycle) on the host bus. The MC68VZ328 accesses to the S1D13708 may occur asyn-
chronously to the display update.
• BS# is not used for the Dragonball host bus interface and must be tied high to IO V
DD
.