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Page 134 Epson Research and Development
Vancouver Design Center
S1D13708 Hardware Functional Specification
X39A-A-001-02 Issue Date: 02/03/07
bit 5 Hardware Video Invert Enable
This bit allows the Video Invert feature to be controlled using the General Purpose IO pin
GPIO0. This option is not available if configured for a HR-TFT, D-TFD, TFT Type 2,
or TFT Type 3 as GPIO0 is used as an LCD control signal by these panels.
When this bit = 0, GPIO0 has no effect on the video data.
When this bit = 1, video data may be inverted via GPIO0.
Note
The S1D13708 requires some configuration before the hardware video invert feature
can be enabled.
• CNF3 must be set to 1 at RESET#
• GPIO Pin Input Enable (REG[A9h] bit 7) must be set to 1
• GPIO0 Pin IO Configuration (REG[A8h] bit 0) must be set to 0
If Hardware Video Invert is not available, the video invert function can be controlled by
software using REG[70h] bit 4. The following table summarizes the video invert options
available.
Note
Video data is inverted after the Look-Up Table.
bit 4 Software Video Invert
When this bit = 0, video data is normal.
When this bit = 1, video data is inverted.
See Table 8-8: “Inverse Video Mode Select Options”.
Note
Video data is inverted after the Look-Up Table
Table 8-8: Inverse Video Mode Select Options
Hardware Video
Invert Enable
Software Video
Invert
GPIO0 Video Data
00XNormal
0 1 X Inverse
1X0Normal
1 X 1 Inverse